Analog-Baseband Architectures And Circuits For Multistandard by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

With the prior few decade efforts on lithography and integrated-circuit (IC) applied sciences, very reasonably cheap microsystems were effectively built for lots of varied purposes. the craze in instant communications is towards making a networkubiquitous period within the years yet to come. Many exceptional possibilities and demanding situations, akin to layout for multi-standardability and low-voltage (LV) compliance, are speedily turning into the mainstream instructions in wireless-IC learn and improvement, on condition that the previous can supply the simplest connectivity between diversified networks, whereas the latter can facilitate the know-how migration into the sub-1-V nanoscale regimes for additional price and tool relief.

Analog-Baseband Architecturees and Circuits presents architectural and circuit strategies for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the publication experiences the actual layer requirements of recent instant verbal exchange criteria, provides the basic tradeoffs all for transceiver structure choice, and gives case reports of the state of the art multistandard transceivers, the place the foremost thoughts strengthened are highlighted and mentioned. A statistical precis (with a hundred+ references mentioned) of such a lot used transmitter and receiver architectures for contemporary conversation criteria is equipped. the entire references are citied from the top boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The moment half specializes in the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection procedure is disclosed. It, in the course of the reconfiguration of receiver and transmitter analog basebands, permits not just a leisure of the RF frequency synthesizer’s and native oscillator’s layout standards, but additionally an effective multistandard compliance by means of synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the main is tested in few layout examples. one among them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but additionally encompasses a flexible-IF topology, a different 3D-stack floorplan, and a selected layout method for prime testability and routability.

The 3rd half bargains with the circuit layout. as well as the methodical description of many LV circuit thoughts, three tailormade LV-robust practical blocks are provided. They comprise: 1) a double-quadrature-downconversion clear out (DQDF) – it realizes at the same time clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it deals a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon quarter required for knowing a wide time consistent on chip whereas maximizing its highpass-pole switchability for quick dc-offset transient.

The final half offers experimental result of the three tailored development blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS technique. formerly untold on-/off-chip co-setup for either full-chip and construction blocks measurements are defined. not just the construction blocks have effectively prolonged the cutting-edge boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been to date the lowest-voltage-reported resolution for IEEE 802.11a/b/g WLAN receivers.

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2004. 77] D. , “A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 299–301, June 2005. 78] P. 4GHz,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 92–93, Feb. 2003. 79] S. 1 to 5GHz CMOS DSSS UWB Transceiver for WPANs,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 214–215, Feb. 2005. 80] B.

Different from 14 Analog-Baseband Architectures and Circuits Case-III, the dc-offset cancellation for the PGA and LPF is relaxed in its highpass pole frequency. 5 Comparison of different receiver architectures Table 2-1 summarizes and compares the presented RX architectures. Their characteristics determine their appropriateness for use in modern wireless communication systems, as presented in Section 4. Table 2-1. Summary of different RX architectures RX Architecture Advantages Disadvantages Superheterodyne + Reliable performance + Flexible frequency plan + No DC offset and 1/f noise Image-Rejection (Hartley and Weaver) + Low cost + No DC offset and 1/f noise + High integratability – Expensive and bulky, high power – Difficult to share the SAW filters for multistandard – Quadrature RF-to-BB downconversion – Suffer from first and secondary images – Narrowband (Hartley) – High I/Q matching Zero-IF Low-IF 3.

11b and in receive and transmit modes. However, the TX–RX turn-around time becomes an issue by permitting the use of time-continuous dc-offset cancellation loop, which results in a long settling time. Y. Jung’s TXR achieves a very small area by using a direct-conversion for both RX and TX. 28 Analog-Baseband Architectures and Circuits A lowpass filter with different bandwidths is much area- and power-efficient than the realization of a polyphase/lowpass reconfigurable filter. The dc offset is suppressed by building a dc-offset cancellation loop in each PGA.

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