Asynchronous Circuits by Janusz A. Brzozowski

By Janusz A. Brzozowski

Although asynchronous circuits date again to the early Nineteen Fifties many of the electronic circuits in use this day are synchronous simply because, routinely, asynchronous circuits were considered as obscure and layout. in recent times, notwithstanding, there was an exceptional surge of curiosity in asynchronous circuits, principally during the improvement of recent asynchronous layout methodologies.
This booklet presents a entire idea of asynchronous circuits, together with modelling, research, simulation, specification, verification, and an creation to their layout. it's in response to classes given to graduate scholars and should be compatible for desktop scientists and engineers focused on the study and improvement of asynchronous designs.

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Define a mapping I I: En - Bn as follows: 1. The expressions 0, 1, Xl,"" Xn are mapped to the functions IXII,· .. , IXnl, respectively, where IXil is defined by Thus the function tuple. 2. IXil 101, 111, selects the ith component of its argument n- I(E+F)I d~f (IEI+IFI), The mapping II assigns to each expression E E En a unique Boolean function lEI E Bn. However, there is an infinite number of expressions denoting a given function. This can be seen as follows. First, every Boolean function has a canonical sum-of-products expression, in which each product is a product of complemented and uncomplemented variables [25, 58J.

In general, given a gate circuit, we obtain its circuit graph as follows. First, there is an input vertex Xi for every external input, and a gate vertex for every gate. For every input vertex Xi there is an input-delay vertex 2 Xi and an edge from Xi to Xi. For every input i of every gate g in the circuit there is a wire vertex z. There is an edge from the wire vertex Z to the gate vertex corresponding to the gate g. If the input i is connected to an external input Xj, there is an edge from the input-delay vertex Xj to the wire vertex z.

Classes of Gate Circuits 49 Consequently, Y2 = Xl (X 2 X 3 )+X I X 2 = ... = X 2 +X I X 3 · Similarly, Y3 Y4 Y5 = = X I +X2 , X I X 2 +X3 , X I +X3 . Since, after a certain delay, all the gate outputs are uniquely determined by the external inputs, the gate circuit is combinational, despite the fact that it contains feedback. It should be clear that the Boolean function model does not take into account all of the properties of a physical gate. For example, physical gates have delays associated with their operation.

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