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**Read or Download Foundation of Switching Theory and Logic Design: (As Per JNTU Syllabus) PDF**

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**Additional info for Foundation of Switching Theory and Logic Design: (As Per JNTU Syllabus)**

**Example text**

MSB < r/2) then the result is +ve and representing the correct magnitude. Thus, no post processing is required. 2. , MSB > r/2) = then the result is –ve and correct magnitude of which must be obtained by post processing (Step 7). Step 7. Post Processing and Result Declaration By the step 6(a) – 1 and the step 6(b) – 1 we know that if the result is positive (+ve) it represents the correct magnitude whether it is signed or unsigned arithmetic. However, the negative results are not showing correct magnitudes so post processing in principle is needed for declaration of negative results.

If the parity of the received data is changed (from that of transmitted parity), it means that at least one bit has changed their value during transmission. Though the parity code is meant for single error detection, it can detect any odd number of errors. However, in both the cases the original codeword can not be found. If there is even combination of errors (means some bits are changed but parity remains same) it remains undetected. Longitudinal Redundancy Check (LRC) In LRC, a block of bits is organised in rows and columns (table).

Since final carry is not generated in step 2, the result is negative and is in 2’s complement form. So we must take 2’s complement of result obtained in step 2 to find correct magnitude of result. 3 Signed Binary Representation Untill now we have discussed representation of unsigned (or positive) numbers, except one or two places. In computer systems sign (+ve or –ve) of a number should also be represented by binary bits. The accepted convention is to use 1 for negative sign and 0 for positive sign.