By Apple Computer
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Extra resources for Inside Macintosh, Volume III
The locations of the SCC control and data lines are given in the following table as offsets from the constant sccWBase for writes, or sccRBase for reads. These base addresses are also available in the global variables SCCWr and SCCRd. The SCC is on the upper byte of the data bus, so ^ou must use only even-addressed byte reads (a byte read of an odd SCC read address tries to reset the entire SCC). When writing, however, you must use only o
This places the ROM starting at the normal ROM location $400000, and a duplicate image of the same ROM starting at address 0 (where RAM normally is), while RAM is placed starting at $600000. Under this mapping, the Macintosh software executes out of the normal ROM locations above $400000, but the MC68QP0 can obtain some critical low-memory vectors from the ROM image it finds at address 0. Next, a memory test and several other system tests take place. After the system is fully tested and initialized, the software clears the VIA's overlay bit, mapping the system RAM back where it belongs, starting at address 0.
When sending data to the Macintosh, the keyboard clock transmits eight 330-usec cycles (160 usee low, 170 usee high) on the normally high clock line. sec before the falling edge of the clock line and maintains it for 330 usee. The data bit is clocked into the Macintosh's "VTA shift register on the rising edge of the keyboard clock cycle. When the Macintosh sends data to the keyboard, the keyboard clock transmits eight 400-usec cycles (180 usee low, 220 usee high) on the clock line. On the falling edge of the keyboard clock cycle, the Macintosh places the data bit on the data line and holds it there for 400 usee.